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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-04 09:40:19 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | f54020eb8155371725ab75b0fc5c419287eca084 (patch) | |
| tree | 65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/cpu/base.cc | |
| parent | 2113b21996d086dab32b9fd388efe3df241bfbd2 (diff) | |
| download | gem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz | |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/base.cc')
| -rw-r--r-- | src/cpu/base.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index c576f1def..1a497db9a 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -318,7 +318,7 @@ BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) assert(tid < numThreads); AddressMonitor &monitor = addressMonitor[tid]; - Request req; + RequestPtr req; Addr addr = monitor.vAddr; int block_size = cacheLineSize(); uint64_t mask = ~((uint64_t)(block_size - 1)); @@ -330,13 +330,13 @@ BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) if (secondAddr > addr) size = secondAddr - addr; - req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); + req->setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); // translate to physical address - Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); + Fault fault = dtb->translateAtomic(req, tc, BaseTLB::Read); assert(fault == NoFault); - monitor.pAddr = req.getPaddr() & mask; + monitor.pAddr = req->getPaddr() & mask; monitor.waiting = true; DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", |