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authorAnthony Gutierrez <atgutier@umich.edu>2012-08-15 10:38:08 -0400
committerAnthony Gutierrez <atgutier@umich.edu>2012-08-15 10:38:08 -0400
commit0b3897fc90901953e9d016466c37ab507f85023c (patch)
tree0e8b1fec8d7c4871686903d573e9fd0fd8734d1e /src/cpu/base.cc
parent5a648f2074caad8aee97e03f27e8eecc527a2cba (diff)
downloadgem5-0b3897fc90901953e9d016466c37ab507f85023c.tar.xz
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation.
Diffstat (limited to 'src/cpu/base.cc')
-rw-r--r--src/cpu/base.cc10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 4017140a5..893b0e06b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -385,8 +385,7 @@ void
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
-
- _cpuId = oldCPU->cpuId();
+ assert(_cpuId == oldCPU->cpuId());
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
@@ -418,11 +417,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(old_itb_port);
SlavePort &slavePort = old_itb_port->getSlavePort();
new_itb_port->bind(slavePort);
+ old_itb_port->unBind();
}
if (new_dtb_port && !new_dtb_port->isConnected()) {
assert(old_dtb_port);
SlavePort &slavePort = old_dtb_port->getSlavePort();
new_dtb_port->bind(slavePort);
+ old_dtb_port->unBind();
}
// Checker whether or not we have to transfer CheckerCPU
@@ -444,17 +445,20 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(old_checker_itb_port);
SlavePort &slavePort = old_checker_itb_port->getSlavePort();;
new_checker_itb_port->bind(slavePort);
+ old_checker_itb_port->unBind();
}
if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
assert(old_checker_dtb_port);
SlavePort &slavePort = old_checker_dtb_port->getSlavePort();;
new_checker_dtb_port->bind(slavePort);
+ old_checker_dtb_port->unBind();
}
}
}
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
+ oldCPU->interrupts = NULL;
if (FullSystem) {
for (ThreadID i = 0; i < size; ++i)
@@ -469,10 +473,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
// CPU.
if (!getInstPort().isConnected()) {
getInstPort().bind(oldCPU->getInstPort().getSlavePort());
+ oldCPU->getInstPort().unBind();
}
if (!getDataPort().isConnected()) {
getDataPort().bind(oldCPU->getDataPort().getSlavePort());
+ oldCPU->getDataPort().unBind();
}
}