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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-07 15:15:11 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-07 15:15:11 -0400 |
| commit | ea11c7bdbefc8eb640f875cdf91a6d6bed398ec4 (patch) | |
| tree | 3af6e347d31fffe724122db63ebff97aaf819c3e /src/cpu/base.cc | |
| parent | 1ccfdb442ff34f9f2b38ee7716b7baee99a397c2 (diff) | |
| download | gem5-ea11c7bdbefc8eb640f875cdf91a6d6bed398ec4.tar.xz | |
Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory
configs/test/test.py:
Update to use new cpu getPort functionality
src/cpu/base.cc:
Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
Make sure the cache recognizes all port names
--HG--
extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
Diffstat (limited to 'src/cpu/base.cc')
| -rw-r--r-- | src/cpu/base.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 0b9c80591..548f012df 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -63,7 +63,7 @@ BaseCPU::BaseCPU(Params *p) params(p), number_of_threads(p->numberOfThreads), system(p->system) #else BaseCPU::BaseCPU(Params *p) - : SimObject(p->name), clock(p->clock), params(p), + : MemObject(p->name), clock(p->clock), params(p), number_of_threads(p->numberOfThreads), system(p->system) #endif { |