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authorAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:38 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:38 -0600
commit8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch)
tree0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/cpu/base.cc
parent7e104a1af235823e3d641a972ea920937f7ec67d (diff)
downloadgem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python.
Diffstat (limited to 'src/cpu/base.cc')
-rw-r--r--src/cpu/base.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 977769126..d8585567d 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -120,6 +120,8 @@ CPUProgressEvent::description() const
BaseCPU::BaseCPU(Params *p)
: MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
+ _instMasterId(p->system->getMasterId(name() + ".inst")),
+ _dataMasterId(p->system->getMasterId(name() + ".data")),
interrupts(p->interrupts),
numThreads(p->numThreads), system(p->system),
phase(p->phase)