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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-19 16:58:33 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-02-07 16:14:39 +0000 |
| commit | f4e27c3ff56894e738bd2a975646b5a07d9ea75c (patch) | |
| tree | 7ed54c037502d2b97fb4a6eaaca46be18468f0f2 /src/cpu/base.cc | |
| parent | b72d69c5caa382902fc200086e861e92ef883163 (diff) | |
| download | gem5-f4e27c3ff56894e738bd2a975646b5a07d9ea75c.tar.xz | |
arch-arm: Fault when dc ivac is executed from EL0
A previous change enabled execution of dc ivac from EL0 when
SCTLR_EL1.UCI=1. The Arm ARM specifies that dc ivac is the only data
cache maintenance operation by VA that cannot be executed from
EL0. This changeset essential reverts the change:
8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1
Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7823
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/base.cc')
0 files changed, 0 insertions, 0 deletions