diff options
author | Jose Marinho <jose.marinho@arm.com> | 2017-10-19 18:45:26 +0100 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-20 17:34:49 +0000 |
commit | 7bd68dbc368e2d877f6159f5d0039198983e459a (patch) | |
tree | 520b10f7f9f5c9eb1e912f29bacf1a10bcff87d5 /src/cpu/base.cc | |
parent | c0d613adb4eca09c32aca1cc90f04c29574f69c6 (diff) | |
download | gem5-7bd68dbc368e2d877f6159f5d0039198983e459a.tar.xz |
cpu: Make automatic transition to OFF optional
Add the power_gating_on_idle option to control whether a core
automatically enters the power gated state. The default behaviour is
to transition to clock gated when idle, but not to power gated. When
this option is set to true, the core automatically transitions to the
power gated state after a configurable latency.
Change-Id: Ida98c7fc532de4140d0e511c25613769b47b3702
Reviewed-on: https://gem5-review.googlesource.com/5741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/base.cc')
-rw-r--r-- | src/cpu/base.cc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 78cf4196c..af55ee1d6 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -138,6 +138,7 @@ BaseCPU::BaseCPU(Params *p, bool is_checker) addressMonitor(p->numThreads), syscallRetryLatency(p->syscallRetryLatency), pwrGatingLatency(p->pwr_gating_latency), + powerGatingOnIdle(p->power_gating_on_idle), enterPwrGatingEvent([this]{ enterPwrGating(); }, name()) { // if Python did not provide a valid ID, do it here @@ -493,7 +494,8 @@ BaseCPU::schedulePowerGatingEvent() return; } - if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED) { + if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED && + powerGatingOnIdle) { assert(!enterPwrGatingEvent.scheduled()); // Schedule a power gating event when clock gated for the specified // amount of time @@ -536,8 +538,12 @@ BaseCPU::suspendContext(ThreadID thread_num) // All CPU threads suspended, enter lower power state for the CPU ClockedObject::pwrState(Enums::PwrState::CLK_GATED); - //Schedule power gating event when clock gated for a configurable cycles - schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); + // If pwrGatingLatency is set to 0 then this mechanism is disabled + if (powerGatingOnIdle) { + // Schedule power gating event when clock gated for pwrGatingLatency + // cycles + schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); + } } void |