diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-02-16 08:56:40 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-02-16 08:56:40 -0800 |
| commit | 89a7fb03934b3e38c7d8b2c4818794b3ec874fdf (patch) | |
| tree | 53a9b0877112908b1f6c3e5cad256a9b63a5de16 /src/cpu/base.cc | |
| parent | 6923282fb5a9ba6af14d19be094839eefe1c34be (diff) | |
| download | gem5-89a7fb03934b3e38c7d8b2c4818794b3ec874fdf.tar.xz | |
Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
Diffstat (limited to 'src/cpu/base.cc')
| -rw-r--r-- | src/cpu/base.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 06fcebad8..0ef206d90 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -344,8 +344,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) assert(newTC->threadId() == oldTC->threadId()); system->replaceThreadContext(newTC, newTC->contextId()); - if (DTRACE(Context)) + /* This code no longer works since the zero register (e.g., + * r31 on Alpha) doesn't necessarily contain zero at this + * point. + if (DTRACE(Context)) ThreadContext::compare(oldTC, newTC); + */ } #if FULL_SYSTEM |