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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 15:59:21 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 15:59:21 -0700 |
| commit | 2736086d7c67a24d9eb87827a22a2b352e342ba2 (patch) | |
| tree | 13828ffb0528a82a7f6c10a40e2976ac03898eb3 /src/cpu/base.hh | |
| parent | 6fd4eff68f53ec1cd9194581bfa223bfbaa2d83d (diff) | |
| download | gem5-2736086d7c67a24d9eb87827a22a2b352e342ba2.tar.xz | |
CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
Diffstat (limited to 'src/cpu/base.hh')
| -rw-r--r-- | src/cpu/base.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh index a12c98ab0..b0eece2a1 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -35,6 +35,7 @@ #include <vector> #include "arch/isa_traits.hh" +#include "arch/microcode_rom.hh" #include "base/statistics.hh" #include "config/full_system.hh" #include "sim/eventq.hh" @@ -103,6 +104,8 @@ class BaseCPU : public MemObject */ Tick nextCycle(Tick begin_tick); + TheISA::MicrocodeRom microcodeRom; + #if FULL_SYSTEM protected: // uint64_t interrupts[TheISA::NumInterruptLevels]; |