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authorGabe Black <gblack@eecs.umich.edu>2007-03-15 02:52:51 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-03-15 02:52:51 +0000
commit32368a2bd62409b303b0fcbe796fc94e4902657d (patch)
treeaf146159b4488dc9bf1c581162452a8de06a3d16 /src/cpu/base.hh
parentff90b8c1aa99711eeb55c5eba29519f77cbc041c (diff)
parenta2b56088fb4d12aee73ecfeaba88cfa46f98567e (diff)
downloadgem5-32368a2bd62409b303b0fcbe796fc94e4902657d.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge --HG-- extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
Diffstat (limited to 'src/cpu/base.hh')
-rw-r--r--src/cpu/base.hh8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 7167bfde0..4d8300186 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -34,11 +34,11 @@
#include <vector>
+#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "config/full_system.hh"
#include "sim/eventq.hh"
#include "mem/mem_object.hh"
-#include "arch/isa_traits.hh"
#if FULL_SYSTEM
#include "arch/interrupts.hh"
@@ -50,6 +50,11 @@ class ThreadContext;
class System;
class Port;
+namespace TheISA
+{
+ class Predecoder;
+}
+
class CPUProgressEvent : public Event
{
protected:
@@ -125,6 +130,7 @@ class BaseCPU : public MemObject
protected:
std::vector<ThreadContext *> threadContexts;
+ std::vector<TheISA::Predecoder *> predecoders;
public: