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authorAkash Bagdia <akash.bagdia@arm.com>2014-05-09 18:58:46 -0400
committerAkash Bagdia <akash.bagdia@arm.com>2014-05-09 18:58:46 -0400
commit2b1a01ee6ccda9f046b1ceb13c90ee0635473959 (patch)
tree1877032b428dce5a8cbfd69f0f974b1015184a0d /src/cpu/base.hh
parente940bac278a877699238f9c70748762ea9379db4 (diff)
downloadgem5-2b1a01ee6ccda9f046b1ceb13c90ee0635473959.tar.xz
cpu, arm: Allow the specification of a socket field
Allow the specification of a socket ID for every core that is reflected in the MPIDR field in ARM systems. This allows studying multi-socket / cluster systems with ARM CPUs.
Diffstat (limited to 'src/cpu/base.hh')
-rw-r--r--src/cpu/base.hh10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 321b785a2..cc3f861cc 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -101,6 +101,13 @@ class BaseCPU : public MemObject
// therefore no setCpuId() method is provided
int _cpuId;
+ /** Each cpu will have a socket ID that corresponds to its physical location
+ * in the system. This is usually used to bucket cpu cores under single DVFS
+ * domain. This information may also be required by the OS to identify the
+ * cpu core grouping (as in the case of ARM via MPIDR register)
+ */
+ const uint32_t _socketId;
+
/** instruction side request id that must be placed in all requests */
MasterID _instMasterId;
@@ -145,6 +152,9 @@ class BaseCPU : public MemObject
/** Reads this CPU's ID. */
int cpuId() const { return _cpuId; }
+ /** Reads this CPU's Socket ID. */
+ uint32_t socketId() const { return _socketId; }
+
/** Reads this CPU's unique data requestor ID */
MasterID dataMasterId() { return _dataMasterId; }
/** Reads this CPU's unique instruction requestor ID */