MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.

1 files changed, 7 insertions, 8 deletions

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 149d26aa3..145b014aa 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -117,7 +117,7 @@ class BaseCPU : public MemObject
      * both atomic and timing access is to panic and the corresponding
      * subclasses have to override these methods.
      */
-    class CpuPort : public Port
+    class CpuPort : public MasterPort
     {
       public:
 
@@ -128,7 +128,7 @@ class BaseCPU : public MemObject
          * @param _name structural owner of this port
          */
         CpuPort(const std::string& _name, MemObject* _owner) :
-            Port(_name, _owner)
+            MasterPort(_name, _owner)
         { }
 
       protected:
@@ -141,8 +141,6 @@ class BaseCPU : public MemObject
 
         void recvFunctional(PacketPtr pkt);
 
-        void recvRangeChange();
-
     };
 
   public:
@@ -172,11 +170,11 @@ class BaseCPU : public MemObject
     MasterID instMasterId() { return _instMasterId; }
 
     /**
-     * Get a port on this MemObject. This method is virtual to allow
+     * Get a master port on this MemObject. This method is virtual to allow
      * the subclasses of the BaseCPU to override it. All CPUs have a
      * data and instruction port, but the Atomic CPU (in its current
      * form) adds a port directly connected to the memory and has to
-     * override getPort.
+     * override getMasterPort.
      *
      * This method uses getDataPort and getInstPort to resolve the two
      * ports.
@@ -184,9 +182,10 @@ class BaseCPU : public MemObject
      * @param if_name the port name
      * @param idx ignored index
      *
-     * @return a pointer to the port with the given name
+     * @return a reference to the port with the given name
      */
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual MasterPort &getMasterPort(const std::string &if_name,
+                                      int idx = -1);
 
 //    Tick currentTick;
     inline Tick frequency() const { return SimClock::Frequency / clock; }