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| author | Korey Sewell <ksewell@umich.edu> | 2011-03-26 09:23:52 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-03-26 09:23:52 -0400 |
| commit | e0fdd86fd90d16ec7b7f9e2f81a12c2653919a27 (patch) | |
| tree | 0e0cd264b48dbf264234e572b55d38f9ffd04a9e /src/cpu/base.hh | |
| parent | 48b58b3332251670432db2cc7832b80eb2787bda (diff) | |
| download | gem5-e0fdd86fd90d16ec7b7f9e2f81a12c2653919a27.tar.xz | |
mips: cleanup ISA-specific code
***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
anyway.
Diffstat (limited to 'src/cpu/base.hh')
| -rw-r--r-- | src/cpu/base.hh | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh index a56f3db24..8557b5bd5 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -239,8 +239,6 @@ class BaseCPU : public MemObject */ ThreadID numThreads; - TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core - /** * Vector of per-thread instruction-based event queues. Used for * scheduling events based on number of instructions committed by |