CPU: Round-two unifying instr/data CPU ports across models

This patch continues the unification of how the different CPU models
create and share their instruction and data ports. Most importantly,
it forces every CPU to have an instruction and a data port, and gives
these ports explicit getters in the BaseCPU (getDataPort and
getInstPort). The patch helps in simplifying the code, make
assumptions more explicit, andfurther ease future patches related to
the CPU ports.

The biggest changes are in the in-order model (that was not modified
in the previous unification patch), which now moves the ports from the
CacheUnit to the CPU. It also distinguishes the instruction fetch and
load-store unit from the rest of the resources, and avoids the use of
indices and casting in favour of keeping track of these two units
explicitly (since they are always there anyways). The atomic, timing
and O3 model simply return references to their already existing ports.

1 files changed, 34 insertions, 1 deletions

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 74c1a8762..8728a6e07 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -63,7 +63,6 @@ class BranchPred;
 class CheckerCPU;
 class ThreadContext;
 class System;
-class Port;
 
 namespace TheISA
 {
@@ -147,6 +146,23 @@ class BaseCPU : public MemObject
     };
 
   public:
+
+    /**
+     * Purely virtual method that returns a reference to the data
+     * port. All subclasses must implement this method.
+     *
+     * @return a reference to the data port
+     */
+    virtual CpuPort &getDataPort() = 0;
+
+    /**
+     * Purely virtual method that returns a reference to the instruction
+     * port. All subclasses must implement this method.
+     *
+     * @return a reference to the instruction port
+     */
+    virtual CpuPort &getInstPort() = 0;
+
     /** Reads this CPU's ID. */
     int cpuId() { return _cpuId; }
 
@@ -155,6 +171,23 @@ class BaseCPU : public MemObject
     /** Reads this CPU's unique instruction requestor ID */
     MasterID instMasterId() { return _instMasterId; }
 
+    /**
+     * Get a port on this MemObject. This method is virtual to allow
+     * the subclasses of the BaseCPU to override it. All CPUs have a
+     * data and instruction port, but the Atomic CPU (in its current
+     * form) adds a port directly connected to the memory and has to
+     * override getPort.
+     *
+     * This method uses getDataPort and getInstPort to resolve the two
+     * ports.
+     *
+     * @param if_name the port name
+     * @param idx ignored index
+     *
+     * @return a pointer to the port with the given name
+     */
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
+
 //    Tick currentTick;
     inline Tick frequency() const { return SimClock::Frequency / clock; }
     inline Tick ticks(int numCycles) const { return clock * numCycles; }