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authorGabe Black <gblack@eecs.umich.edu>2006-11-03 02:25:39 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-03 02:25:39 -0500
commitc8fc116c7636893517254f785707eba1726d3265 (patch)
tree7d3ed56234bf2f40d77395673b90ad7e69292165 /src/cpu/base.hh
parentfa918329000c3661a4c6840f952c3247522eb826 (diff)
downloadgem5-c8fc116c7636893517254f785707eba1726d3265.tar.xz
Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the
--HG-- extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
Diffstat (limited to 'src/cpu/base.hh')
-rw-r--r--src/cpu/base.hh18
1 files changed, 10 insertions, 8 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 75e0d86af..207473d80 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -40,6 +40,10 @@
#include "mem/mem_object.hh"
#include "arch/isa_traits.hh"
+#if FULL_SYSTEM
+#include "arch/interrupts.hh"
+#endif
+
class BranchPred;
class CheckerCPU;
class ThreadContext;
@@ -75,8 +79,9 @@ class BaseCPU : public MemObject
#if FULL_SYSTEM
protected:
- uint64_t interrupts[TheISA::NumInterruptLevels];
- uint64_t intstatus;
+// uint64_t interrupts[TheISA::NumInterruptLevels];
+// uint64_t intstatus;
+ TheISA::Interrupts interrupts;
public:
virtual void post_interrupt(int int_num, int index);
@@ -85,14 +90,11 @@ class BaseCPU : public MemObject
bool checkInterrupts;
bool check_interrupt(int int_num) const {
- if (int_num > TheISA::NumInterruptLevels)
- panic("int_num out of bounds\n");
-
- return interrupts[int_num] != 0;
+ return interrupts.check_interrupt(int_num);
}
- bool check_interrupts() const { return intstatus != 0; }
- uint64_t intr_status() const { return intstatus; }
+ bool check_interrupts() const { return interrupts.check_interrupts(); }
+ //uint64_t intr_status() const { return interrupts.intr_status(); }
class ProfileEvent : public Event
{