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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /src/cpu/base.hh | |
parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'src/cpu/base.hh')
-rw-r--r-- | src/cpu/base.hh | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 0286ac45b..2a57c01ba 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -207,41 +207,45 @@ class BaseCPU : public MemObject TheISA::MicrocodeRom microcodeRom; protected: - TheISA::Interrupts *interrupts; + std::vector<TheISA::Interrupts*> interrupts; public: TheISA::Interrupts * - getInterruptController() + getInterruptController(ThreadID tid) { - return interrupts; + if (interrupts.empty()) + return NULL; + + assert(interrupts.size() > tid); + return interrupts[tid]; } virtual void wakeup() = 0; void - postInterrupt(int int_num, int index) + postInterrupt(ThreadID tid, int int_num, int index) { - interrupts->post(int_num, index); + interrupts[tid]->post(int_num, index); if (FullSystem) wakeup(); } void - clearInterrupt(int int_num, int index) + clearInterrupt(ThreadID tid, int int_num, int index) { - interrupts->clear(int_num, index); + interrupts[tid]->clear(int_num, index); } void - clearInterrupts() + clearInterrupts(ThreadID tid) { - interrupts->clearAll(); + interrupts[tid]->clearAll(); } bool checkInterrupts(ThreadContext *tc) const { - return FullSystem && interrupts->checkInterrupts(tc); + return FullSystem && interrupts[tc->threadId()]->checkInterrupts(tc); } class ProfileEvent : public Event |