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| author | Gabe Black <gabeblack@google.com> | 2019-09-02 21:26:12 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-19 01:45:48 +0000 |
| commit | ae390c629f2a10fd6a1c2eb50b7d3510d6e091da (patch) | |
| tree | 51f12635838755ef7519bea1c72bfb96e0214336 /src/cpu/base.hh | |
| parent | 1c047f8b92f5708bbef50d24cf47902d5da313e3 (diff) | |
| download | gem5-ae390c629f2a10fd6a1c2eb50b7d3510d6e091da.tar.xz | |
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/base.hh')
| -rw-r--r-- | src/cpu/base.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 383ae8185..cb23cb1ba 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -54,7 +54,7 @@ #if THE_ISA == NULL_ISA #include "arch/null/cpu_dummy.hh" #else -#include "arch/interrupts.hh" +#include "arch/generic/interrupts.hh" #include "arch/isa_traits.hh" #include "arch/microcode_rom.hh" #include "base/statistics.hh" @@ -219,10 +219,10 @@ class BaseCPU : public ClockedObject TheISA::MicrocodeRom microcodeRom; protected: - std::vector<TheISA::Interrupts*> interrupts; + std::vector<BaseInterrupts*> interrupts; public: - TheISA::Interrupts * + BaseInterrupts * getInterruptController(ThreadID tid) { if (interrupts.empty()) |