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author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2017-07-07 14:13:11 +0100 |
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committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-05-11 12:48:58 +0000 |
commit | c58cb8c9dbeef377da180f1fdaaa1c0eadf85550 (patch) | |
tree | 7591abeb888d8c8e645332749bcaea627628f9bf /src/cpu/base.hh | |
parent | d0e4cdc9c36466a3dbef8c9f9f509cce8f1a6c34 (diff) | |
download | gem5-c58cb8c9dbeef377da180f1fdaaa1c0eadf85550.tar.xz |
cpu,mem: Add support for partial loads/stores and wide mem. accesses
This changeset adds support for partial (or masked) loads/stores, i.e.
loads/stores that can disable accesses to individual bytes within the
target address range. In addition, this changeset extends the code to
crack memory accesses across most CPU models (TimingSimpleCPU still
TBD), so that arbitrarily wide memory accesses are supported. These
changes are required for supporting ISAs with wide vectors.
Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>
- Tiago Muck <tiago.muck@arm.com>
Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/base.hh')
-rw-r--r-- | src/cpu/base.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh index f013a3e02..3d679f172 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -175,9 +175,9 @@ class BaseCPU : public ClockedObject uint32_t socketId() const { return _socketId; } /** Reads this CPU's unique data requestor ID */ - MasterID dataMasterId() { return _dataMasterId; } + MasterID dataMasterId() const { return _dataMasterId; } /** Reads this CPU's unique instruction requestor ID */ - MasterID instMasterId() { return _instMasterId; } + MasterID instMasterId() const { return _instMasterId; } /** * Get a port on this CPU. All CPUs have a data and |