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authorKevin Lim <ktlim@umich.edu>2006-06-14 13:12:41 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-14 13:12:41 -0400
commit5d11e8bff6a7feed1e126b9b28df3a69b21e94e4 (patch)
tree4debb45a51570c9e57ea134962701c7dc41894ea /src/cpu/base_dyn_inst.cc
parent7709e6ba93be4b67b22e2f3f9c853a3e1ab4458b (diff)
downloadgem5-5d11e8bff6a7feed1e126b9b28df3a69b21e94e4.tar.xz
Minor code cleanup of BaseDynInst.
src/cpu/base_dyn_inst.cc: src/cpu/base_dyn_inst.hh: Minor code cleanup by putting several bools into a bitset instead. src/cpu/o3/commit_impl.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob_impl.hh: Changed around some things in BaseDynInst. --HG-- extra : convert_revision : 1db363d69a863cc8744cc9f9ec542ade8472eb42
Diffstat (limited to 'src/cpu/base_dyn_inst.cc')
-rw-r--r--src/cpu/base_dyn_inst.cc35
1 files changed, 5 insertions, 30 deletions
diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst.cc
index e3829297d..4bcd59848 100644
--- a/src/cpu/base_dyn_inst.cc
+++ b/src/cpu/base_dyn_inst.cc
@@ -99,39 +99,18 @@ BaseDynInst<Impl>::initVars()
memData = NULL;
effAddr = 0;
physEffAddr = 0;
- storeSize = 0;
readyRegs = 0;
instResult.integer = 0;
- // May want to turn this into a bit vector or something.
- completed = false;
- resultReady = false;
- canIssue = false;
- issued = false;
- executed = false;
- canCommit = false;
- committed = false;
- squashed = false;
- squashedInIQ = false;
- squashedInLSQ = false;
- squashedInROB = false;
+ status.reset();
+
eaCalcDone = false;
memOpDone = false;
+
lqIdx = -1;
sqIdx = -1;
- reachedCommit = false;
-
- blockingInst = false;
- recoverInst = false;
-
- iqEntry = false;
- robEntry = false;
-
- serializeBefore = false;
- serializeAfter = false;
- serializeHandled = false;
// Eventually make this a parameter.
threadNumber = 0;
@@ -294,7 +273,7 @@ void
BaseDynInst<Impl>::markSrcRegReady()
{
if (++readyRegs == numSrcRegs()) {
- canIssue = true;
+ status.set(CanIssue);
}
}
@@ -302,13 +281,9 @@ template <class Impl>
void
BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
{
- ++readyRegs;
-
_readySrcRegIdx[src_idx] = true;
- if (readyRegs == numSrcRegs()) {
- canIssue = true;
- }
+ markSrcRegReady();
}
template <class Impl>