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authorKevin Lim <ktlim@umich.edu>2006-06-12 19:04:42 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-12 19:04:42 -0400
commit4acb283496c7667bf0161f45e578c702d2cf8dbc (patch)
tree43a88dbf3a835170f685cc95c2ca315c6a1d710b /src/cpu/base_dyn_inst.cc
parentfbf3a82c5c358d75acd9a97ad1dcef9796b83c96 (diff)
downloadgem5-4acb283496c7667bf0161f45e578c702d2cf8dbc.tar.xz
Clean up/shift some code around.
src/cpu/base_dyn_inst.cc: Clean up some code and update. src/cpu/base_dyn_inst.hh: Clean up some code and update with more descriptive function names. src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: Remove unused parameters. src/cpu/o3/commit_impl.hh: Remove unused parameters, also set squashCounter directly to the counted number of squashes. src/cpu/o3/fetch_impl.hh: Update for function name changes. src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: Remove unused parameter, move some code into a function. --HG-- extra : convert_revision : 45abd77ad43dde2e93c2e53c4738c90ba8352a1d
Diffstat (limited to 'src/cpu/base_dyn_inst.cc')
-rw-r--r--src/cpu/base_dyn_inst.cc68
1 files changed, 6 insertions, 62 deletions
diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst.cc
index 30fa10a6b..e3829297d 100644
--- a/src/cpu/base_dyn_inst.cc
+++ b/src/cpu/base_dyn_inst.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -103,6 +103,8 @@ BaseDynInst<Impl>::initVars()
readyRegs = 0;
+ instResult.integer = 0;
+
// May want to turn this into a bit vector or something.
completed = false;
resultReady = false;
@@ -242,31 +244,7 @@ template <class Impl>
void
BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
{
- // Need to create a MemReq here so we can do a translation. This
- // will casue a TLB miss trap if necessary... not sure whether
- // that's the best thing to do or not. We don't really need the
- // MemReq otherwise, since wh64 has no functional effect.
-/*
- MemReqPtr req = new MemReq(addr, thread->getXCProxy(), size, flags);
- req->asid = asid;
-
- fault = cpu->translateDataWriteReq(req);
-
- if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
- // Record key MemReq parameters so we can generate another one
- // just like it for the timing access without calling translate()
- // again (which might mess up the TLB).
- effAddr = req->vaddr;
- physEffAddr = req->paddr;
- memReqFlags = req->flags;
- } else {
- // ignore faults & accesses to uncacheable space... treat as no-op
- effAddr = physEffAddr = MemReq::inval_addr;
- }
-
- storeSize = size;
- storeData = 0;
-*/
+ // Not currently supported.
}
/**
@@ -276,22 +254,7 @@ template <class Impl>
Fault
BaseDynInst<Impl>::copySrcTranslate(Addr src)
{
-/*
- MemReqPtr req = new MemReq(src, thread->getXCProxy(), 64);
- req->asid = asid;
-
- // translate to physical address
- Fault fault = cpu->translateDataReadReq(req);
-
- if (fault == NoFault) {
- thread->copySrcAddr = src;
- thread->copySrcPhysAddr = req->paddr;
- } else {
- thread->copySrcAddr = 0;
- thread->copySrcPhysAddr = 0;
- }
- return fault;
-*/
+ // Not currently supported.
return NoFault;
}
@@ -302,26 +265,7 @@ template <class Impl>
Fault
BaseDynInst<Impl>::copy(Addr dest)
{
-/*
- uint8_t data[64];
- FunctionalMemory *mem = thread->mem;
- assert(thread->copySrcPhysAddr);
- MemReqPtr req = new MemReq(dest, thread->getXCProxy(), 64);
- req->asid = asid;
-
- // translate to physical address
- Fault fault = cpu->translateDataWriteReq(req);
-
- if (fault == NoFault) {
- Addr dest_addr = req->paddr;
- // Need to read straight from memory since we have more than 8 bytes.
- req->paddr = thread->copySrcPhysAddr;
- mem->read(req, data);
- req->paddr = dest_addr;
- mem->write(req, data);
- }
- return fault;
-*/
+ // Not currently supported.
return NoFault;
}