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authorKevin Lim <ktlim@umich.edu>2006-06-16 17:53:33 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-16 17:53:33 -0400
commit4e07f6ca52828247fe1741b1e6c5269ad5291187 (patch)
treeaf786c3cfcdd5640b5840ffdfab64bb55b9e49f9 /src/cpu/base_dyn_inst.cc
parent51a5b826373e2c08ba173854a19597d59e0e3c90 (diff)
parent0bbd909f02e72a321a65b933104c5ef1e157116b (diff)
downloadgem5-4e07f6ca52828247fe1741b1e6c5269ad5291187.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 488b9a9965dd86ca73dc9e510e5b3122cbd357f9
Diffstat (limited to 'src/cpu/base_dyn_inst.cc')
-rw-r--r--src/cpu/base_dyn_inst.cc39
1 files changed, 7 insertions, 32 deletions
diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst.cc
index e3829297d..5e2a6392a 100644
--- a/src/cpu/base_dyn_inst.cc
+++ b/src/cpu/base_dyn_inst.cc
@@ -71,8 +71,8 @@ my_hash_t thishash;
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
Addr pred_PC, InstSeqNum seq_num,
- FullCPU *cpu)
- : staticInst(machInst), traceData(NULL), cpu(cpu)/*, xc(cpu->xcBase())*/
+ ImplCPU *cpu)
+ : staticInst(machInst), traceData(NULL), cpu(cpu)
{
seqNum = seq_num;
@@ -99,39 +99,18 @@ BaseDynInst<Impl>::initVars()
memData = NULL;
effAddr = 0;
physEffAddr = 0;
- storeSize = 0;
readyRegs = 0;
instResult.integer = 0;
- // May want to turn this into a bit vector or something.
- completed = false;
- resultReady = false;
- canIssue = false;
- issued = false;
- executed = false;
- canCommit = false;
- committed = false;
- squashed = false;
- squashedInIQ = false;
- squashedInLSQ = false;
- squashedInROB = false;
+ status.reset();
+
eaCalcDone = false;
memOpDone = false;
+
lqIdx = -1;
sqIdx = -1;
- reachedCommit = false;
-
- blockingInst = false;
- recoverInst = false;
-
- iqEntry = false;
- robEntry = false;
-
- serializeBefore = false;
- serializeAfter = false;
- serializeHandled = false;
// Eventually make this a parameter.
threadNumber = 0;
@@ -294,7 +273,7 @@ void
BaseDynInst<Impl>::markSrcRegReady()
{
if (++readyRegs == numSrcRegs()) {
- canIssue = true;
+ status.set(CanIssue);
}
}
@@ -302,13 +281,9 @@ template <class Impl>
void
BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
{
- ++readyRegs;
-
_readySrcRegIdx[src_idx] = true;
- if (readyRegs == numSrcRegs()) {
- canIssue = true;
- }
+ markSrcRegReady();
}
template <class Impl>