ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.

This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.

1 files changed, 37 insertions, 93 deletions

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index e9b7daa4a..bc6f59407 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -38,6 +38,7 @@
 #include <string>
 
 #include "arch/faults.hh"
+#include "arch/utility.hh"
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
@@ -241,36 +242,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Records changes to result? */
     bool recordResult;
 
-    /** PC of this instruction. */
-    Addr PC;
-
-    /** Micro PC of this instruction. */
-    Addr microPC;
-
     /** Did this instruction execute, or is it predicated false */
     bool predicate;
 
   protected:
-    /** Next non-speculative PC.  It is not filled in at fetch, but rather
-     *  once the target of the branch is truly known (either decode or
-     *  execute).
-     */
-    Addr nextPC;
-
-    /** Next non-speculative NPC. Target PC for Mips or Sparc. */
-    Addr nextNPC;
+    /** PC state for this instruction. */
+    TheISA::PCState pc;
 
-    /** Next non-speculative micro PC. */
-    Addr nextMicroPC;
-
-    /** Predicted next PC. */
-    Addr predPC;
-
-    /** Predicted next NPC. */
-    Addr predNPC;
-
-    /** Predicted next microPC */
-    Addr predMicroPC;
+    /** Predicted PC state after this instruction. */
+    TheISA::PCState predPC;
 
     /** If this is a branch that was predicted taken */
     bool predTaken;
@@ -386,27 +366,23 @@ class BaseDynInst : public FastAlloc, public RefCounted
     }
     /** BaseDynInst constructor given a binary instruction.
      *  @param staticInst A StaticInstPtr to the underlying instruction.
-     *  @param PC The PC of the instruction.
-     *  @param pred_PC The predicted next PC.
-     *  @param pred_NPC The predicted next NPC.
+     *  @param pc The PC state for the instruction.
+     *  @param predPC The predicted next PC state for the instruction.
      *  @param seq_num The sequence number of the instruction.
      *  @param cpu Pointer to the instruction's CPU.
      */
-    BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
-            Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
-            InstSeqNum seq_num, ImplCPU *cpu);
+    BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc,
+                TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
 
     /** BaseDynInst constructor given a binary instruction.
      *  @param inst The binary instruction.
-     *  @param PC The PC of the instruction.
-     *  @param pred_PC The predicted next PC.
-     *  @param pred_NPC The predicted next NPC.
+     *  @param _pc The PC state for the instruction.
+     *  @param _predPC The predicted next PC state for the instruction.
      *  @param seq_num The sequence number of the instruction.
      *  @param cpu Pointer to the instruction's CPU.
      */
-    BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
-            Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
-            InstSeqNum seq_num, ImplCPU *cpu);
+    BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc,
+                TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
 
     /** BaseDynInst constructor given a StaticInst pointer.
      *  @param _staticInst The StaticInst for this BaseDynInst.
@@ -443,45 +419,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
      */
     bool doneTargCalc() { return false; }
 
-    /** Returns the next PC.  This could be the speculative next PC if it is
-     *  called prior to the actual branch target being calculated.
-     */
-    Addr readNextPC() { return nextPC; }
-
-    /** Returns the next NPC.  This could be the speculative next NPC if it is
-     *  called prior to the actual branch target being calculated.
-     */
-    Addr readNextNPC()
-    {
-#if ISA_HAS_DELAY_SLOT
-        return nextNPC;
-#else
-        return nextPC + sizeof(TheISA::MachInst);
-#endif
-    }
-
-    Addr readNextMicroPC()
-    {
-        return nextMicroPC;
-    }
-
     /** Set the predicted target of this current instruction. */
-    void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
-            Addr predicted_MicroPC)
+    void setPredTarg(const TheISA::PCState &_predPC)
     {
-        predPC = predicted_PC;
-        predNPC = predicted_NPC;
-        predMicroPC = predicted_MicroPC;
+        predPC = _predPC;
     }
 
+    const TheISA::PCState &readPredTarg() { return predPC; }
+
     /** Returns the predicted PC immediately after the branch. */
-    Addr readPredPC() { return predPC; }
+    Addr predInstAddr() { return predPC.instAddr(); }
 
     /** Returns the predicted PC two instructions after the branch */
-    Addr readPredNPC() { return predNPC; }
+    Addr predNextInstAddr() { return predPC.nextInstAddr(); }
 
     /** Returns the predicted micro PC after the branch */
-    Addr readPredMicroPC() { return predMicroPC; }
+    Addr predMicroPC() { return predPC.microPC(); }
 
     /** Returns whether the instruction was predicted taken or not. */
     bool readPredTaken()
@@ -497,9 +450,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Returns whether the instruction mispredicted. */
     bool mispredicted()
     {
-        return readPredPC() != readNextPC() ||
-            readPredNPC() != readNextNPC() ||
-            readPredMicroPC() != readNextMicroPC();
+        TheISA::PCState tempPC = pc;
+        TheISA::advancePC(tempPC, staticInst);
+        return !(tempPC == predPC);
     }
 
     //
@@ -576,7 +529,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
     OpClass opClass() const { return staticInst->opClass(); }
 
     /** Returns the branch target address. */
-    Addr branchTarget() const { return staticInst->branchTarget(PC); }
+    TheISA::PCState branchTarget() const
+    { return staticInst->branchTarget(pc); }
 
     /** Returns the number of source registers. */
     int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
@@ -773,30 +727,20 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Returns whether or not this instruction is squashed in the ROB. */
     bool isSquashedInROB() const { return status[SquashedInROB]; }
 
-    /** Read the PC of this instruction. */
-    const Addr readPC() const { return PC; }
+    /** Read the PC state of this instruction. */
+    const TheISA::PCState pcState() const { return pc; }
 
-    /**Read the micro PC of this instruction. */
-    const Addr readMicroPC() const { return microPC; }
+    /** Set the PC state of this instruction. */
+    const void pcState(const TheISA::PCState &val) { pc = val; }
 
-    /** Set the next PC of this instruction (its actual target). */
-    void setNextPC(Addr val)
-    {
-        nextPC = val;
-    }
+    /** Read the PC of this instruction. */
+    const Addr instAddr() const { return pc.instAddr(); }
 
-    /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
-    void setNextNPC(Addr val)
-    {
-#if ISA_HAS_DELAY_SLOT
-        nextNPC = val;
-#endif
-    }
+    /** Read the PC of the next instruction. */
+    const Addr nextInstAddr() const { return pc.nextInstAddr(); }
 
-    void setNextMicroPC(Addr val)
-    {
-        nextMicroPC = val;
-    }
+    /**Read the micro PC of this instruction. */
+    const Addr microPC() const { return pc.microPC(); }
 
     bool readPredicate()
     {
@@ -895,7 +839,7 @@ BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
                              unsigned size, unsigned flags)
 {
     reqMade = true;
-    Request *req = new Request(asid, addr, size, flags, this->PC,
+    Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(),
                                thread->contextId(), threadNumber);
 
     Request *sreqLow = NULL;
@@ -956,7 +900,7 @@ BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
     }
 
     reqMade = true;
-    Request *req = new Request(asid, addr, size, flags, this->PC,
+    Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(),
                                thread->contextId(), threadNumber);
 
     Request *sreqLow = NULL;