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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-27 15:48:22 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-11 15:07:52 +0000 |
| commit | c3bd8eb1214cbebbc92c7958b80aa06913bce3ba (patch) | |
| tree | 6df53d30662ba49d93a1b90e3bfd1826bdb6726e /src/cpu/base_dyn_inst.hh | |
| parent | f73caae20fed7b4500a724ac85c20b637ee353a1 (diff) | |
| download | gem5-c3bd8eb1214cbebbc92c7958b80aa06913bce3ba.tar.xz | |
cpu: Fix coding style (byteEnable->byte_enable)
Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index c228357ce..85ad54404 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -304,11 +304,11 @@ class BaseDynInst : public ExecContext, public RefCounted } Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector<bool>& byteEnable = std::vector<bool>()); + const std::vector<bool>& byte_enable = std::vector<bool>()); Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector<bool>& byteEnable = std::vector<bool>()); + const std::vector<bool>& byte_enable = std::vector<bool>()); Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op); @@ -963,25 +963,26 @@ template<class Impl> Fault BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector<bool>& byteEnable) + const std::vector<bool>& byte_enable) { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); return cpu->pushRequest( dynamic_cast<typename DynInstPtr::PtrType>(this), /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr, - byteEnable); + byte_enable); } template<class Impl> Fault BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector<bool>& byteEnable) + const std::vector<bool>& byte_enable) { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); return cpu->pushRequest( dynamic_cast<typename DynInstPtr::PtrType>(this), - /* st */ false, data, size, addr, flags, res, nullptr, byteEnable); + /* st */ false, data, size, addr, flags, res, nullptr, + byte_enable); } template<class Impl> |