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author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-10-23 13:51:52 +0100 |
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committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-05-11 09:34:27 +0000 |
commit | d0e4cdc9c36466a3dbef8c9f9f509cce8f1a6c34 (patch) | |
tree | 231e5efecbf42e376b5175affddb88304f485013 /src/cpu/base_dyn_inst.hh | |
parent | c4bc23453133751a1a5858743e6b1266f735d3dc (diff) | |
download | gem5-d0e4cdc9c36466a3dbef8c9f9f509cce8f1a6c34.tar.xz |
cpu: Add a memory access predicate
This changeset introduces a new predicate to guard memory accesses.
The most immediate use for this is to allow proper handling of
predicated-false vector contiguous loads and predicated-false
micro-ops of vector gather loads (added in separate changesets).
Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17991
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index f1c782956..4084241bd 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -135,6 +135,7 @@ class BaseDynInst : public ExecContext, public RefCounted EffAddrValid, RecordResult, Predicate, + MemAccPredicate, PredTaken, IsStrictlyOrdered, ReqMade, @@ -851,6 +852,18 @@ class BaseDynInst : public ExecContext, public RefCounted } } + bool + readMemAccPredicate() const + { + return instFlags[MemAccPredicate]; + } + + void + setMemAccPredicate(bool val) + { + instFlags[MemAccPredicate] = val; + } + /** Sets the ASID. */ void setASID(short addr_space_id) { asid = addr_space_id; } short getASID() { return asid; } |