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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-04 09:40:19 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
commit | f54020eb8155371725ab75b0fc5c419287eca084 (patch) | |
tree | 65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/cpu/base_dyn_inst.hh | |
parent | 2113b21996d086dab32b9fd388efe3df241bfbd2 (diff) | |
download | gem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index e94f500ea..2c08a3c67 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -304,12 +304,12 @@ class BaseDynInst : public ExecContext, public RefCounted Request::Flags flags, uint64_t *res); /** Splits a request in two if it crosses a dcache block. */ - void splitRequest(RequestPtr req, RequestPtr &sreqLow, + void splitRequest(const RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh); /** Initiate a DTB address translation. */ - void initiateTranslation(RequestPtr req, RequestPtr sreqLow, - RequestPtr sreqHigh, uint64_t *res, + void initiateTranslation(const RequestPtr &req, const RequestPtr &sreqLow, + const RequestPtr &sreqHigh, uint64_t *res, BaseTLB::Mode mode); /** Finish a DTB address translation. */ @@ -902,8 +902,9 @@ BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, sreqLow = savedSreqLow; sreqHigh = savedSreqHigh; } else { - req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), - thread->contextId()); + req = std::make_shared<Request>( + asid, addr, size, flags, masterId(), + this->pc.instAddr(), thread->contextId()); req->taskId(cpu->taskId()); @@ -921,10 +922,7 @@ BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, instFlags[EffAddrValid] = true; if (cpu->checker) { - if (reqToVerify != NULL) { - delete reqToVerify; - } - reqToVerify = new Request(*req); + reqToVerify = std::make_shared<Request>(*req); } fault = cpu->read(req, sreqLow, sreqHigh, lqIdx); } else { @@ -958,8 +956,9 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, sreqLow = savedSreqLow; sreqHigh = savedSreqHigh; } else { - req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), - thread->contextId()); + req = std::make_shared<Request>( + asid, addr, size, flags, masterId(), + this->pc.instAddr(), thread->contextId()); req->taskId(cpu->taskId()); @@ -976,10 +975,7 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, instFlags[EffAddrValid] = true; if (cpu->checker) { - if (reqToVerify != NULL) { - delete reqToVerify; - } - reqToVerify = new Request(*req); + reqToVerify = std::make_shared<Request>(*req); } fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); } @@ -989,7 +985,7 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, template<class Impl> inline void -BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, +BaseDynInst<Impl>::splitRequest(const RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh) { // Check to see if the request crosses the next level block boundary. @@ -1006,8 +1002,10 @@ BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, template<class Impl> inline void -BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, - RequestPtr sreqHigh, uint64_t *res, +BaseDynInst<Impl>::initiateTranslation(const RequestPtr &req, + const RequestPtr &sreqLow, + const RequestPtr &sreqHigh, + uint64_t *res, BaseTLB::Mode mode) { translationStarted(true); |