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author | Iru Cai <mytbk920423@gmail.com> | 2019-04-03 10:29:37 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:59:17 +0800 |
commit | c0d7cca1d9895f1c3476ce9864584eb4fb2e6ee9 (patch) | |
tree | 3a1cb356c61cc6366d20c46353ed494d8e49ba92 /src/cpu/base_dyn_inst.hh | |
parent | cb5562bb15f32e9040eccb57271d86fddc614230 (diff) | |
download | gem5-c0d7cca1d9895f1c3476ce9864584eb4fb2e6ee9.tar.xz |
check loads using tainted registers, set USL dst as tainted
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 6684a4765..3ddf25095 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -480,11 +480,22 @@ class BaseDynInst : public ExecContext, public RefCounted void taintDestRegs(void) { - for (auto dstreg: _destRegIdx) { + for (size_t i = 0; i < numDestRegs(); i++) { + auto dstreg = _destRegIdx[i]; cpu->setTaint(dstreg); } } + bool srcTainted(void) + { + bool result = false; + for (size_t i = 0; i < numSrcRegs(); i++) { + auto src = _srcRegIdx[i]; + result |= cpu->regTainted(src); + } + return result; + } + /** Renames a source logical register to the physical register which * has/will produce that logical register's result. * @todo: add in whether or not the source register is ready. |