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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/base_dyn_inst.hh | |
parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz |
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 515df6821..5b54679c9 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -99,19 +99,10 @@ class BaseDynInst : public ExecContext, public RefCounted union Result { uint64_t integer; double dbl; - - // I am assuming that vector register type is different from the two - // types used above. Else it seems useless to have a separate typedef - // for vector registers. - VectorReg vector; - void set(uint64_t i) { integer = i; } void set(double d) { dbl = d; } - void set(const VectorReg &v) { vector = v; } - void get(uint64_t& i) { i = integer; } void get(double& d) { d = dbl; } - void get(VectorReg& v) { v = vector; } }; protected: @@ -530,9 +521,6 @@ class BaseDynInst : public ExecContext, public RefCounted bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } bool isInteger() const { return staticInst->isInteger(); } bool isFloating() const { return staticInst->isFloating(); } - bool isVector() const { return staticInst->isVector(); } - bool isCC() const { return staticInst->isCC(); } - bool isControl() const { return staticInst->isControl(); } bool isCall() const { return staticInst->isCall(); } bool isReturn() const { return staticInst->isReturn(); } @@ -562,11 +550,6 @@ class BaseDynInst : public ExecContext, public RefCounted bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } bool isMicroBranch() const { return staticInst->isMicroBranch(); } - void printFlags(std::ostream &outs, const std::string &separator) const - { staticInst->printFlags(outs, separator); } - - std::string getName() const { return staticInst->getName(); } - /** Temporarily sets this instruction as a serialize before instruction. */ void setSerializeBefore() { status.set(SerializeBefore); } @@ -613,8 +596,6 @@ class BaseDynInst : public ExecContext, public RefCounted int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } - int8_t numVectorDestRegs() const - { return staticInst->numVectorDestRegs(); } /** Returns the logical register index of the i'th destination register. */ RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } @@ -674,13 +655,6 @@ class BaseDynInst : public ExecContext, public RefCounted setResult<uint64_t>(val); } - /** Records a vector register being set to a value. */ - void setVectorRegOperand(const StaticInst *si, int idx, - const VectorReg &val) - { - setResult<const VectorReg &>(val); - } - /** Records that one of the source registers is ready. */ void markSrcRegReady(); |