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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-07-02 22:35:04 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-07-02 22:35:04 -0700 |
| commit | 3a1428365a479db70d893e62e37c1dd302067d4a (patch) | |
| tree | 04f070345857d9a3fc70cb4b9f2c498284983615 /src/cpu/base_dyn_inst.hh | |
| parent | 2e7426664a254688e7cf926b902cb8c535a106dd (diff) | |
| download | gem5-3a1428365a479db70d893e62e37c1dd302067d4a.tar.xz | |
ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 53b2c9b96..f0d36cc83 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -124,10 +124,10 @@ class BaseDynInst : public FastAlloc, public RefCounted cpu->demapPage(vaddr, asn); } - Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); + Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); - Fault writeBytes(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res); + Fault writeMem(uint8_t *data, unsigned size, + Addr addr, unsigned flags, uint64_t *res); /** Splits a request in two if it crosses a dcache block. */ void splitRequest(RequestPtr req, RequestPtr &sreqLow, @@ -841,8 +841,8 @@ class BaseDynInst : public FastAlloc, public RefCounted template<class Impl> Fault -BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, - unsigned size, unsigned flags) +BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, + unsigned size, unsigned flags) { reqMade = true; Request *req = NULL; @@ -893,8 +893,8 @@ BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, template<class Impl> Fault -BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res) +BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, + Addr addr, unsigned flags, uint64_t *res) { if (traceData) { traceData->setAddr(addr); |