diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-01 17:12:43 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-01 17:12:43 -0700 |
| commit | abe18be544014bee31d586bf8b26ab5b622b70b7 (patch) | |
| tree | ad4059302f30b79257cb50cb8e51c5da38c6418c /src/cpu/base_dyn_inst.hh | |
| parent | edeb8f39a7c3cbcf428743aca3017fa42865b04a (diff) | |
| parent | d8501ec17c590a0c6f5be92e121381667ca726b6 (diff) | |
| download | gem5-abe18be544014bee31d586bf8b26ab5b622b70b7.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 40611abe6..3158aa9cf 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -291,18 +291,18 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Returns whether the instruction was predicted taken or not. */ bool predTaken() -#if THE_ISA == ALPHA_ISA - { return predPC != (PC + sizeof(MachInst)); } -#else +#if ISA_HAS_DELAY_SLOT { return predPC != (nextPC + sizeof(MachInst)); } +#else + { return predPC != (PC + sizeof(MachInst)); } #endif /** Returns whether the instruction mispredicted. */ bool mispredicted() -#if THE_ISA == ALPHA_ISA - { return predPC != nextPC; } -#else +#if ISA_HAS_DELAY_SLOT { return predPC != nextNPC; } +#else + { return predPC != nextPC; } #endif // // Instruction types. Forward checks to StaticInst object. |