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author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-10-16 16:04:08 +0100 |
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committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-01-30 16:57:54 +0000 |
commit | 25474167e5b247d1b91fbf802c5b396a63ae705e (patch) | |
tree | b509597b23d792734f55c33b8125eebfbd9cd3a5 /src/cpu/base_dyn_inst.hh | |
parent | c6f5db8743f19b02a38146d9cf2a829883387008 (diff) | |
download | gem5-25474167e5b247d1b91fbf802c5b396a63ae705e.tar.xz |
arch,cpu: Add vector predicate registers
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.
Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index d81b58bdf..b87fd8b4e 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -584,6 +584,11 @@ class BaseDynInst : public ExecContext, public RefCounted { return staticInst->numVecElemDestRegs(); } + int8_t + numVecPredDestRegs() const + { + return staticInst->numVecPredDestRegs(); + } /** Returns the logical register index of the i'th destination register. */ const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } @@ -638,6 +643,16 @@ class BaseDynInst : public ExecContext, public RefCounted InstResult::ResultType::VecElem)); } } + + /** Predicate result. */ + template<typename T> + void setVecPredResult(T&& t) + { + if (instFlags[RecordResult]) { + instResult.push(InstResult(std::forward<T>(t), + InstResult::ResultType::VecPredReg)); + } + } /** @} */ /** Records an integer register being set to a value. */ @@ -672,6 +687,13 @@ class BaseDynInst : public ExecContext, public RefCounted setVecElemResult(val); } + /** Record a vector register being set to a value */ + void setVecPredRegOperand(const StaticInst *si, int idx, + const VecPredRegContainer& val) + { + setVecPredResult(val); + } + /** Records that one of the source registers is ready. */ void markSrcRegReady(); |