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| author | Gabe Black <gabeblack@google.com> | 2018-10-13 00:54:32 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-16 20:27:47 +0000 |
| commit | cf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e (patch) | |
| tree | 75505d60b69951ec0a99ca82e8621803c95d921d /src/cpu/base_dyn_inst.hh | |
| parent | 0c4515ce1ff2a4e40d243df734af2a67cb8b1ad1 (diff) | |
| download | gem5-cf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e.tar.xz | |
cpu: dev: sim: gpu-compute: Banish some ISA specific register types.
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.
Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index ae2911c2d..c2a14089a 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -649,7 +649,7 @@ class BaseDynInst : public ExecContext, public RefCounted /** @} */ /** Records an integer register being set to a value. */ - void setIntRegOperand(const StaticInst *si, int idx, IntReg val) + void setIntRegOperand(const StaticInst *si, int idx, RegVal val) { setScalarResult(val); } @@ -669,7 +669,7 @@ class BaseDynInst : public ExecContext, public RefCounted /** Records an fp register being set to an integer value. */ void - setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) + setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) { setScalarResult(val); } |