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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-10-08 14:48:24 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-10-08 14:48:24 -0700 |
| commit | 5df93cc1cd5ce8272032ad1cbf5265b5fdb4713f (patch) | |
| tree | e3b4acbe3c0df3f7e73afb81e087c9420fb9b430 /src/cpu/base_dyn_inst_impl.hh | |
| parent | 911381321b294fa5a8d2dd77eaabc7473ffe5e6f (diff) | |
| download | gem5-5df93cc1cd5ce8272032ad1cbf5265b5fdb4713f.tar.xz | |
Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().
--HG--
extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
Diffstat (limited to 'src/cpu/base_dyn_inst_impl.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index f2109e88d..d6cdff5c5 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -193,7 +193,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags) // note this is a local, not BaseDynInst::fault Fault trans_fault = cpu->translateDataReadReq(req); - if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) { + if (trans_fault == NoFault && !(req->isUncacheable())) { // It's a valid address to cacheable space. Record key MemReq // parameters so we can generate another one just like it for // the timing access without calling translate() again (which |