Two fixes:

1. Requests are handled more properly now.  They assume the memory system takes control of the request upon sending out an access.
2. load-load ordering is maintained.

src/cpu/base_dyn_inst.hh:
    Update how requests are handled.  The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.

    Also include some functions to allow certain status bits to be cleared.
src/cpu/base_dyn_inst_impl.hh:
    Update how requests are handled.  The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.
src/cpu/o3/fetch_impl.hh:
    General correctness fixes.  retryPkt is not necessarily always set, so handle it properly.  Also consider the cache unblocked only when recvRetry is called.
src/cpu/o3/lsq_unit.hh:
    Handle requests a little more correctly.  Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system.

    Also be sure to not store-load forward from an uncacheable store.
src/cpu/o3/lsq_unit_impl.hh:
    Check to make sure load-load ordering was maintained.

    Also handle requests a little more correctly.

--HG--
extra : convert_revision : e86bead2886d02443cf77bf7a7a1492845e1690f

1 files changed, 4 insertions, 6 deletions

diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index c3d71e428..a1c866336 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -92,11 +92,13 @@ template <class Impl>
 void
 BaseDynInst<Impl>::initVars()
 {
-    req = NULL;
     memData = NULL;
     effAddr = 0;
+    effAddrValid = false;
     physEffAddr = 0;
 
+    isUncacheable = false;
+    reqMade = false;
     readyRegs = 0;
 
     instResult.integer = 0;
@@ -140,10 +142,6 @@ BaseDynInst<Impl>::initVars()
 template <class Impl>
 BaseDynInst<Impl>::~BaseDynInst()
 {
-    if (req) {
-        delete req;
-    }
-
     if (memData) {
         delete [] memData;
     }
@@ -271,7 +269,7 @@ void
 BaseDynInst<Impl>::markSrcRegReady()
 {
     if (++readyRegs == numSrcRegs()) {
-        status.set(CanIssue);
+        setCanIssue();
     }
 }