Add in support for LL/SC in the O3 CPU. Needs to be fully tested.

src/cpu/base_dyn_inst.hh:
    Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code).
src/cpu/base_dyn_inst_impl.hh:
    Add variable to track if the result of the instruction should be recorded.
src/cpu/o3/alpha/cpu_impl.hh:
    Clear lock flag upon hwrei.
src/cpu/o3/lsq_unit.hh:
    Use ISA specified handling of locked reads.
src/cpu/o3/lsq_unit_impl.hh:
    Use ISA specified handling of locked writes.

--HG--
extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5

1 files changed, 1 insertions, 0 deletions

diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index d6cdff5c5..2f6859de2 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -97,6 +97,7 @@ BaseDynInst<Impl>::initVars()
     readyRegs = 0;
 
     instResult.integer = 0;
+    recordResult = true;
 
     status.reset();