diff options
| author | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-01-31 07:46:03 -0800 |
|---|---|---|
| committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-01-31 07:46:03 -0800 |
| commit | af6aaf258171027af8d3cf0ef86dddff501a3ccb (patch) | |
| tree | 3473845b7217b48dcf43460f0a90ca655a7018ed /src/cpu/base_dyn_inst_impl.hh | |
| parent | ade53def9252a36a39b2c4bd61196355906f0505 (diff) | |
| download | gem5-af6aaf258171027af8d3cf0ef86dddff501a3ccb.tar.xz | |
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.
Diffstat (limited to 'src/cpu/base_dyn_inst_impl.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst_impl.hh | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index a37ec5e25..d2ecd01ff 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -48,6 +48,7 @@ #include "base/cprintf.hh" #include "base/trace.hh" #include "config/the_isa.hh" +#include "config/use_checker.hh" #include "cpu/base_dyn_inst.hh" #include "cpu/exetrace.hh" #include "debug/DynInst.hh" @@ -117,7 +118,6 @@ BaseDynInst<Impl>::initVars() reqMade = false; readyRegs = 0; - instResult.integer = 0; recordResult = true; status.reset(); @@ -157,6 +157,10 @@ BaseDynInst<Impl>::initVars() #ifdef DEBUG cpu->snList.insert(seqNum); #endif + +#if USE_CHECKER + reqToVerify = NULL; +#endif } template <class Impl> @@ -182,6 +186,11 @@ BaseDynInst<Impl>::~BaseDynInst() #ifdef DEBUG cpu->snList.erase(seqNum); #endif + +#if USE_CHECKER + if (reqToVerify) + delete reqToVerify; +#endif // USE_CHECKER } #ifdef DEBUG |