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| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | 92ae620be8b46742042dcfe6dfaf38ecac24ad09 (patch) | |
| tree | 740b871d75a40aa85582ba11aadca144978f2378 /src/cpu/base_dyn_inst_impl.hh | |
| parent | 43c938d23e2b28c7190bd10c470c452676f5cb9d (diff) | |
| download | gem5-92ae620be8b46742042dcfe6dfaf38ecac24ad09.tar.xz | |
ARM: mark msr/mrs instructions as SerializeBefore/After
Since miscellaneous registers bypass wakeup logic, force serialization
to resolve data dependencies through them
* * *
ARM: adding non-speculative/serialize flags for instructions change CPSR
Diffstat (limited to 'src/cpu/base_dyn_inst_impl.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst_impl.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index 7425431db..4fb8490c1 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -321,6 +321,8 @@ template <class Impl> void BaseDynInst<Impl>::markSrcRegReady() { + DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n", + seqNum, readyRegs+1, numSrcRegs(), readyToIssue()); if (++readyRegs == numSrcRegs()) { setCanIssue(); } |