ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.

This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.

On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.

On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.

1 files changed, 0 insertions, 67 deletions

diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index 923b204ce..74f199d5f 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -196,73 +196,6 @@ BaseDynInst<Impl>::dumpSNList()
 
 template <class Impl>
 void
-BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
-{
-    // This is the "functional" implementation of prefetch.  Not much
-    // happens here since prefetches don't affect the architectural
-    // state.
-/*
-    // Generate a MemReq so we can translate the effective address.
-    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
-    req->asid = asid;
-
-    // Prefetches never cause faults.
-    fault = NoFault;
-
-    // note this is a local, not BaseDynInst::fault
-    Fault trans_fault = cpu->translateDataReadReq(req);
-
-    if (trans_fault == NoFault && !(req->isUncacheable())) {
-        // It's a valid address to cacheable space.  Record key MemReq
-        // parameters so we can generate another one just like it for
-        // the timing access without calling translate() again (which
-        // might mess up the TLB).
-        effAddr = req->vaddr;
-        physEffAddr = req->paddr;
-        memReqFlags = req->flags;
-    } else {
-        // Bogus address (invalid or uncacheable space).  Mark it by
-        // setting the eff_addr to InvalidAddr.
-        effAddr = physEffAddr = MemReq::inval_addr;
-    }
-
-    if (traceData) {
-        traceData->setAddr(addr);
-    }
-*/
-}
-
-template <class Impl>
-void
-BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
-{
-    // Not currently supported.
-}
-
-/**
- * @todo Need to find a way to get the cache block size here.
- */
-template <class Impl>
-Fault
-BaseDynInst<Impl>::copySrcTranslate(Addr src)
-{
-    // Not currently supported.
-    return NoFault;
-}
-
-/**
- * @todo Need to find a way to get the cache block size here.
- */
-template <class Impl>
-Fault
-BaseDynInst<Impl>::copy(Addr dest)
-{
-    // Not currently supported.
-    return NoFault;
-}
-
-template <class Impl>
-void
 BaseDynInst<Impl>::dump()
 {
     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());