diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-12 10:58:45 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-12 10:58:45 -0400 |
| commit | 866cfaf9dc596d8547e14bc2133fb962776572a7 (patch) | |
| tree | 19b82a8021533e8bc2e35f14fb0b6a0440756814 /src/cpu/base_dyn_inst_impl.hh | |
| parent | 6a31898a88a9ecced399ccf50636831c21d4a75e (diff) | |
| parent | 78aec04b660544ea7af80d76912b4422c4426602 (diff) | |
| download | gem5-866cfaf9dc596d8547e14bc2133fb962776572a7.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
Diffstat (limited to 'src/cpu/base_dyn_inst_impl.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index f2109e88d..d6cdff5c5 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -193,7 +193,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags) // note this is a local, not BaseDynInst::fault Fault trans_fault = cpu->translateDataReadReq(req); - if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) { + if (trans_fault == NoFault && !(req->isUncacheable())) { // It's a valid address to cacheable space. Record key MemReq // parameters so we can generate another one just like it for // the timing access without calling translate() again (which |