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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
commit | 8615b27174ae06db4665016c877b1e88031af203 (patch) | |
tree | 7b28888f71e7e41e84d4087b6ccb53670e04582b /src/cpu/checker/cpu.cc | |
parent | 76ee011a12ade238d5cbf4b570e1d34d7ba72687 (diff) | |
download | gem5-8615b27174ae06db4665016c877b1e88031af203.tar.xz |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
Diffstat (limited to 'src/cpu/checker/cpu.cc')
-rw-r--r-- | src/cpu/checker/cpu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index ac476e5f4..4d5919cdf 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -155,7 +155,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags) // Need to account for multiple accesses like the Atomic and TimingSimple while (1) { memReq = new Request(0, addr, size, flags, masterId, - thread->pcState().instAddr(), tc->contextId(), 0); + thread->pcState().instAddr(), tc->contextId()); // translate to physical address fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read); @@ -243,7 +243,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size, // Need to account for a multiple access like Atomic and Timing CPUs while (1) { memReq = new Request(0, addr, size, flags, masterId, - thread->pcState().instAddr(), tc->contextId(), 0); + thread->pcState().instAddr(), tc->contextId()); // translate to physical address fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write); |