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author | Andreas Hansson <andreas.hansson@arm.com> | 2015-01-22 05:00:53 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-01-22 05:00:53 -0500 |
commit | f49830ce0ba79c54c65c9c4b25bc3c6184aaf2a9 (patch) | |
tree | 00b2f9f0131ef65a411c9fd81339caecfc946b47 /src/cpu/checker/cpu.cc | |
parent | be3a952394e1f337d1c372448ee099203336181a (diff) | |
download | gem5-f49830ce0ba79c54c65c9c4b25bc3c6184aaf2a9.tar.xz |
mem: Clean up Request initialisation
This patch tidies up how we create and set the fields of a Request. In
essence it tries to use the constructor where possible (as opposed to
setPhys and setVirt), thus avoiding spreading the information across a
number of locations. In fact, setPhys is made private as part of this
patch, and a number of places where we callede setVirt instead uses
the appropriate constructor.
Diffstat (limited to 'src/cpu/checker/cpu.cc')
-rw-r--r-- | src/cpu/checker/cpu.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index f91bad294..d6a8bd032 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -154,8 +154,8 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags) // Need to account for multiple accesses like the Atomic and TimingSimple while (1) { - memReq = new Request(); - memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr()); + memReq = new Request(0, addr, size, flags, masterId, + thread->pcState().instAddr(), tc->contextId(), 0); // translate to physical address fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read); @@ -242,8 +242,8 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size, // Need to account for a multiple access like Atomic and Timing CPUs while (1) { - memReq = new Request(); - memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr()); + memReq = new Request(0, addr, size, flags, masterId, + thread->pcState().instAddr(), tc->contextId(), 0); // translate to physical address fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write); |