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authorGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:27 -0500
committerGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:27 -0500
commit043709fdfab3b6c46f6ef95d1f642cd3c06ee20a (patch)
treeef8bab03f4260b67b57b00844d0245ca1e849ea0 /src/cpu/checker/cpu.cc
parentdf05ffab1289b26aab2a0eb71ee55dcb7f42e5e9 (diff)
downloadgem5-043709fdfab3b6c46f6ef95d1f642cd3c06ee20a.tar.xz
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
Diffstat (limited to 'src/cpu/checker/cpu.cc')
-rw-r--r--src/cpu/checker/cpu.cc25
1 files changed, 14 insertions, 11 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index b21ceeb92..66341b0e0 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -52,6 +52,7 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "params/CheckerCPU.hh"
+#include "sim/full_system.hh"
#include "sim/tlb.hh"
using namespace std;
@@ -84,12 +85,7 @@ CheckerCPU::CheckerCPU(Params *p)
dtb = p->dtb;
systemPtr = NULL;
workload = p->workload;
- // XXX: This is a hack to get this to work some
- thread = new SimpleThread(this, /* thread_num */ 0,
- workload.size() ? workload[0] : NULL, itb, dtb);
-
- tc = thread->getTC();
- threadContexts.push_back(tc);
+ thread = NULL;
updateOnError = true;
}
@@ -103,22 +99,29 @@ CheckerCPU::setSystem(System *system)
{
systemPtr = system;
- thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
+ if (FullSystem) {
+ thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
+ } else {
+ thread = new SimpleThread(this, 0, systemPtr,
+ workload.size() ? workload[0] : NULL,
+ itb, dtb);
+ }
tc = thread->getTC();
threadContexts.push_back(tc);
- delete thread->kernelStats;
thread->kernelStats = NULL;
+ // Thread should never be null after this
+ assert(thread != NULL);
}
void
-CheckerCPU::setIcachePort(Port *icache_port)
+CheckerCPU::setIcachePort(CpuPort *icache_port)
{
icachePort = icache_port;
}
void
-CheckerCPU::setDcachePort(Port *dcache_port)
+CheckerCPU::setDcachePort(CpuPort *dcache_port)
{
dcachePort = dcache_port;
}
@@ -151,7 +154,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
// Need to account for multiple accesses like the Atomic and TimingSimple
while (1) {
memReq = new Request();
- memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
+ memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
// translate to physical address
fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);