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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-27 15:48:22 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-11 15:07:52 +0000 |
| commit | c3bd8eb1214cbebbc92c7958b80aa06913bce3ba (patch) | |
| tree | 6df53d30662ba49d93a1b90e3bfd1826bdb6726e /src/cpu/checker/cpu.cc | |
| parent | f73caae20fed7b4500a724ac85c20b637ee353a1 (diff) | |
| download | gem5-c3bd8eb1214cbebbc92c7958b80aa06913bce3ba.tar.xz | |
cpu: Fix coding style (byteEnable->byte_enable)
Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/checker/cpu.cc')
| -rw-r--r-- | src/cpu/checker/cpu.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 48ee05985..2f020c4a9 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -176,9 +176,9 @@ CheckerCPU::genMemFragmentRequest(Addr frag_addr, int size, Fault CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, - const std::vector<bool>& byteEnable) + const std::vector<bool>& byte_enable) { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); Fault fault = NoFault; bool checked_flags = false; @@ -193,7 +193,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, // Need to account for multiple accesses like the Atomic and TimingSimple while (1) { RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags, - byteEnable, frag_size, + byte_enable, frag_size, size_left); predicate = (mem_req != nullptr); @@ -260,9 +260,9 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, Fault CheckerCPU::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector<bool>& byteEnable) + const std::vector<bool>& byte_enable) { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); Fault fault = NoFault; bool checked_flags = false; @@ -278,7 +278,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size, // Need to account for a multiple access like Atomic and Timing CPUs while (1) { RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags, - byteEnable, frag_size, + byte_enable, frag_size, size_left); predicate = (mem_req != nullptr); |