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authorAndreas Hansson <andreas.hansson@arm.com>2013-03-26 14:46:42 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-03-26 14:46:42 -0400
commit08c1835bef5caa72dc931ed529e4ed3470989d4f (patch)
treec7523438790ccf9d6206fe328291bec468d84b48 /src/cpu/checker/cpu.hh
parent670fc52f1812727457eaf6cb4fca1a520a6a8c20 (diff)
downloadgem5-08c1835bef5caa72dc931ed529e4ed3470989d4f.tar.xz
cpu: Remove CpuPort and use MasterPort in the CPU classes
This patch changes the port in the CPU classes to use MasterPort instead of the derived CpuPort. The functions of the CpuPort are now distributed across the relevant subclasses. The port accessor functions (getInstPort and getDataPort) now return a MasterPort instead of a CpuPort. This simplifies creating derivative CPUs that do not use the CpuPort.
Diffstat (limited to 'src/cpu/checker/cpu.hh')
-rw-r--r--src/cpu/checker/cpu.hh12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6bd2b7e31..19d3420ec 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -104,11 +104,11 @@ class CheckerCPU : public BaseCPU
void setSystem(System *system);
- void setIcachePort(CpuPort *icache_port);
+ void setIcachePort(MasterPort *icache_port);
- void setDcachePort(CpuPort *dcache_port);
+ void setDcachePort(MasterPort *dcache_port);
- CpuPort &getDataPort()
+ MasterPort &getDataPort()
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
@@ -116,7 +116,7 @@ class CheckerCPU : public BaseCPU
return *dcachePort;
}
- CpuPort &getInstPort()
+ MasterPort &getInstPort()
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
@@ -130,8 +130,8 @@ class CheckerCPU : public BaseCPU
System *systemPtr;
- CpuPort *icachePort;
- CpuPort *dcachePort;
+ MasterPort *icachePort;
+ MasterPort *dcachePort;
ThreadContext *tc;