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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
| commit | 219c423f1fb0f9a559bfa87f9812426d5e2c3e29 (patch) | |
| tree | 7980ae867c4642e710af7cd5d0ad7fe51c0b6687 /src/cpu/checker/cpu.hh | |
| parent | a830e63de71e5929b8ff8e334bc872faa9193a8b (diff) | |
| download | gem5-219c423f1fb0f9a559bfa87f9812426d5e2c3e29.tar.xz | |
cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful.
Specifically, made these substitutions:
s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;
Diffstat (limited to 'src/cpu/checker/cpu.hh')
| -rw-r--r-- | src/cpu/checker/cpu.hh | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 19d3420ec..637481706 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -213,13 +213,13 @@ class CheckerCPU : public BaseCPU FloatReg readFloatRegOperand(const StaticInst *si, int idx) { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; + int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; return thread->readFloatReg(reg_idx); } FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; + int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; return thread->readFloatRegBits(reg_idx); } @@ -239,7 +239,7 @@ class CheckerCPU : public BaseCPU void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; + int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; thread->setFloatReg(reg_idx, val); setResult<double>(val); } @@ -247,7 +247,7 @@ class CheckerCPU : public BaseCPU void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; + int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; thread->setFloatRegBits(reg_idx, val); setResult<uint64_t>(val); } @@ -294,14 +294,14 @@ class CheckerCPU : public BaseCPU MiscReg readMiscRegOperand(const StaticInst *si, int idx) { - int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; + int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; return thread->readMiscReg(reg_idx); } void setMiscRegOperand( const StaticInst *si, int idx, const MiscReg &val) { - int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; + int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; return thread->setMiscReg(reg_idx, val); } |