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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
| commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
| tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/cpu/checker/cpu.hh | |
| parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
| download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz | |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/cpu/checker/cpu.hh')
| -rw-r--r-- | src/cpu/checker/cpu.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 6f5125625..54e446932 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -93,6 +93,9 @@ class CheckerCPU : public BaseCPU typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::MiscReg MiscReg; + + /** id attached to all issued requests */ + MasterID masterId; public: virtual void init(); |