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| author | Geoffrey Blake <Geoffrey.Blake@arm.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Geoffrey Blake <Geoffrey.Blake@arm.com> | 2014-01-24 15:29:30 -0600 |
| commit | 9633282fc8f152ba897347d38fa85a7b374e3d1e (patch) | |
| tree | aa619c797ae5aad914639758c71b595cd71ac117 /src/cpu/checker/cpu.hh | |
| parent | 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 (diff) | |
| download | gem5-9633282fc8f152ba897347d38fa85a7b374e3d1e.tar.xz | |
checker: CheckerCPU handling of MiscRegs was incorrect
The CheckerCPU model in pre-v8 code was not checking the
updates to miscellaneous registers due to some methods
for setting misc regs were not instrumented. The v8 patches
exposed this by calling the instrumented misc reg update
methods and then invoking the checker before the main CPU had
updated its misc regs, leading to false positives about
register mismatches. This patch fixes the non-instrumented
misc reg update methods and places calls to the checker in
the proper places in the O3 model.
Diffstat (limited to 'src/cpu/checker/cpu.hh')
| -rw-r--r-- | src/cpu/checker/cpu.hh | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index c49f264f9..9f4c4d58c 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -296,12 +296,14 @@ class CheckerCPU : public BaseCPU void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { + DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); miscRegIdxs.push(misc_reg); return thread->setMiscRegNoEffect(misc_reg, val); } void setMiscReg(int misc_reg, const MiscReg &val) { + DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); miscRegIdxs.push(misc_reg); return thread->setMiscReg(misc_reg, val); } @@ -316,7 +318,7 @@ class CheckerCPU : public BaseCPU const StaticInst *si, int idx, const MiscReg &val) { int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; - return thread->setMiscReg(reg_idx, val); + return this->setMiscReg(reg_idx, val); } #if THE_ISA == MIPS_ISA @@ -392,7 +394,6 @@ class CheckerCPU : public BaseCPU bool changedPC; bool willChangePC; TheISA::PCState newPCState; - bool changedNextPC; bool exitOnError; bool updateOnError; bool warnOnlyOnLoadError; |