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authorKevin Lim <ktlim@umich.edu>2006-06-06 14:06:30 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-06 14:06:30 -0400
commit0f014e4340bb0991716cb0f0feafd48b53e865d7 (patch)
tree0cd92f279e9ce3c002fb109cf6e8acd99e3c3123 /src/cpu/checker/cpu.hh
parent090496bf2d4c0f55f7f5869a374b4ec3826bccbc (diff)
downloadgem5-0f014e4340bb0991716cb0f0feafd48b53e865d7.tar.xz
Fix checker to work in newmem in SE mode.
src/cpu/o3/fetch_impl.hh: Give the checker a pointer to the icachePort. src/cpu/o3/lsq_unit_impl.hh: Give the checker a pointer to the dcachePort. src/mem/request.hh: Allow checking for the scResult being valid prior to accessing it. --HG-- extra : convert_revision : ced4180588d242111ecba4a11586823badd6cf15
Diffstat (limited to 'src/cpu/checker/cpu.hh')
-rw-r--r--src/cpu/checker/cpu.hh16
1 files changed, 14 insertions, 2 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 2f9689028..704580d80 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -108,6 +108,8 @@ class CheckerCPU : public BaseCPU
CheckerCPU(Params *p);
virtual ~CheckerCPU();
+ Process *process;
+
void setMemory(MemObject *mem);
MemObject *memPtr;
@@ -117,6 +119,15 @@ class CheckerCPU : public BaseCPU
System *systemPtr;
#endif
+
+ void setIcachePort(Port *icache_port);
+
+ Port *icachePort;
+
+ void setDcachePort(Port *dcache_port);
+
+ Port *dcachePort;
+
public:
// execution context
CPUExecContext *cpuXC;
@@ -141,8 +152,8 @@ class CheckerCPU : public BaseCPU
// current instruction
MachInst machInst;
- // Refcounted pointer to the one memory request.
- Request *memReq;
+ // Pointer to the one memory request.
+ RequestPtr memReq;
StaticInstPtr curStaticInst;
@@ -334,6 +345,7 @@ class CheckerCPU : public BaseCPU
Result unverifiedResult;
Request *unverifiedReq;
+ uint8_t *unverifiedMemData;
bool changedPC;
bool willChangePC;