cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 23 insertions, 1 deletions

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index a363b6d0f..6d75f7c12 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -94,6 +94,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::MiscReg MiscReg;
+    typedef TheISA::VectorReg VectorReg;
 
     /** id attached to all issued requests */
     MasterID masterId;
@@ -145,10 +146,19 @@ class CheckerCPU : public BaseCPU, public ExecContext
     union Result {
         uint64_t integer;
         double dbl;
+
+        // I am assuming that vector register type is different from the two
+        // types used above.  Else it seems useless to have a separate typedef
+        // for vector registers.
+        VectorReg vector;
+
         void set(uint64_t i) { integer = i; }
         void set(double d) { dbl = d; }
+        void set(const VectorReg &v) { vector = v; }
+
         void get(uint64_t& i) { i = integer; }
         void get(double& d) { d = dbl; }
+        void get(VectorReg& v) { v = vector; }
     };
 
     // ISAs like ARM can have multiple destination registers to check,
@@ -231,6 +241,11 @@ class CheckerCPU : public BaseCPU, public ExecContext
         return thread->readCCReg(reg_idx);
     }
 
+    const VectorReg &readVectorRegOperand(const StaticInst *si, int idx)
+    {
+        return thread->readVectorReg(si->srcRegIdx(idx));
+    }
+
     template <class T>
     void setResult(T t)
     {
@@ -267,6 +282,13 @@ class CheckerCPU : public BaseCPU, public ExecContext
         setResult<uint64_t>(val);
     }
 
+    void setVectorRegOperand(const StaticInst *si, int idx,
+                             const VectorReg &val)
+    {
+        thread->setVectorReg(si->destRegIdx(idx), val);
+        setResult<VectorReg>(val);
+    }
+
     bool readPredicate() { return thread->readPredicate(); }
     void setPredicate(bool val)
     {
@@ -441,7 +463,7 @@ class Checker : public CheckerCPU
     void validateExecution(DynInstPtr &inst);
     void validateState();
 
-    void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
+    void copyResult(DynInstPtr &inst, Result mismatch_val, int start_idx);
     void handlePendingInt();
 
   private: