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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/checker/cpu.hh | |
parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz |
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/checker/cpu.hh')
-rw-r--r-- | src/cpu/checker/cpu.hh | 24 |
1 files changed, 1 insertions, 23 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 6d75f7c12..a363b6d0f 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -94,7 +94,6 @@ class CheckerCPU : public BaseCPU, public ExecContext typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::MiscReg MiscReg; - typedef TheISA::VectorReg VectorReg; /** id attached to all issued requests */ MasterID masterId; @@ -146,19 +145,10 @@ class CheckerCPU : public BaseCPU, public ExecContext union Result { uint64_t integer; double dbl; - - // I am assuming that vector register type is different from the two - // types used above. Else it seems useless to have a separate typedef - // for vector registers. - VectorReg vector; - void set(uint64_t i) { integer = i; } void set(double d) { dbl = d; } - void set(const VectorReg &v) { vector = v; } - void get(uint64_t& i) { i = integer; } void get(double& d) { d = dbl; } - void get(VectorReg& v) { v = vector; } }; // ISAs like ARM can have multiple destination registers to check, @@ -241,11 +231,6 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->readCCReg(reg_idx); } - const VectorReg &readVectorRegOperand(const StaticInst *si, int idx) - { - return thread->readVectorReg(si->srcRegIdx(idx)); - } - template <class T> void setResult(T t) { @@ -282,13 +267,6 @@ class CheckerCPU : public BaseCPU, public ExecContext setResult<uint64_t>(val); } - void setVectorRegOperand(const StaticInst *si, int idx, - const VectorReg &val) - { - thread->setVectorReg(si->destRegIdx(idx), val); - setResult<VectorReg>(val); - } - bool readPredicate() { return thread->readPredicate(); } void setPredicate(bool val) { @@ -463,7 +441,7 @@ class Checker : public CheckerCPU void validateExecution(DynInstPtr &inst); void validateState(); - void copyResult(DynInstPtr &inst, Result mismatch_val, int start_idx); + void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); void handlePendingInt(); private: |