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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
| commit | 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch) | |
| tree | 736bc7ea34184fb103fd836e67672521193602a7 /src/cpu/checker/cpu.hh | |
| parent | f3ba6d20f6070c30418866e627e2418f39b433dd (diff) | |
| download | gem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz | |
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/cpu/checker/cpu.hh')
| -rw-r--r-- | src/cpu/checker/cpu.hh | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 7c01bdc39..0df0147ae 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -47,9 +47,12 @@ // forward declarations #if FULL_SYSTEM +namespace TheISA +{ + class ITB; + class DTB; +} class Processor; -class AlphaITB; -class AlphaDTB; class PhysicalMemory; class RemoteGDB; @@ -96,8 +99,8 @@ class CheckerCPU : public BaseCPU struct Params : public BaseCPU::Params { #if FULL_SYSTEM - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; #else Process *process; #endif @@ -140,8 +143,8 @@ class CheckerCPU : public BaseCPU ThreadContext *tc; - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; #if FULL_SYSTEM Addr dbg_vtophys(Addr addr); @@ -301,19 +304,19 @@ class CheckerCPU : public BaseCPU return thread->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return thread->readMiscRegWithEffect(misc_reg, fault); + return thread->readMiscRegWithEffect(misc_reg); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { result.integer = val; miscRegIdxs.push(misc_reg); return thread->setMiscReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { miscRegIdxs.push(misc_reg); return thread->setMiscRegWithEffect(misc_reg, val); |