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| author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
|---|---|---|
| committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
| commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
| tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/checker/cpu_impl.hh | |
| parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
| download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz | |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/checker/cpu_impl.hh')
| -rw-r--r-- | src/cpu/checker/cpu_impl.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 185fed88e..e18644e0e 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -606,6 +606,9 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val, case FloatRegClass: thread->setFloatRegBits(idx, mismatch_val); break; + case CCRegClass: + thread->setCCReg(idx, mismatch_val); + break; case MiscRegClass: thread->setMiscReg(idx - TheISA::Misc_Reg_Base, mismatch_val); @@ -624,6 +627,9 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val, case FloatRegClass: thread->setFloatRegBits(idx, res); break; + case CCRegClass: + thread->setCCReg(idx, res); + break; case MiscRegClass: // Try to get the proper misc register index for ARM here... thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res); |